1. Field of the Invention
The present invention relates to a semiconductor memory device having an improved pattern layout, and more particularly, to a random access memory (RAM) having an improved pattern arrangement suitable for a more rapid operation.
2. Description of the Related Arts
In general, a semiconductor memory device is composed of a word line which is controlled by a row decoder (X decoder) and a pair of bit lines which are controlled by a column decoder (Y decoder). A memory cell is located at a point of intersection between the word line and the pair of bit lines and is selected to connect with a pair of data buses and then exchanges data through an input/output buffer circuit. Of course, the great many memory cells which constitute a memory cell are arranged in a matrix form and the matrix array is arranged with a minimum pitch width.
In recent years an input/output buffer circuit in a semiconductor memory device often has a multi-bit constitution, for example, a 16K-bits constitution, such as 2K.times.8 bits or 4K.times.4 bits, and so on, a plurality of input/output terminals must be provided in the input/output buffer circuit.
In a random access memory having a multi-bit constitution type of input-output buffer circuit, a column decoder is composed of blocks of column decoders corresponding to a respective cell array. The blocks of column decoders are of the same width and the same pitch as a respective cell array, and are arranged adjacent to a respective corresponding cell array.
As described above, the respective block of column decoders corresponding to a respective cell array is arranged in close contact therewith, so there is not sufficient spare space to provide surplus wiring. Accordingly, the data buses which connect a separate cell array to an input/output buffer circuit including a sense amplifier, a write amplifier, and so on, must make a detour to the column decoders, with the result the chip scale or wiring capacity is increased, causing a reduction in the switching speed.